Location: Mountain View, CA
Company: Microsoft
Principal Machine Learning (ML) Accelerator Silicon Architect to make an impact delivering ML accelerator hardware solutions with their architecture and micro-architecture experience in high-performance, low power ML accelerators or Neural-network Processing Unit (NPU), informed by their past Central Processing Unit (CPU) and/or Graphics Processing Units (GPU) architecture, micro-architecture, or Register Transfer Level (RTL) design.
You will be building an ML accelerator hardware Intellectual Property (IPs) that can be used for inference and training in multiple Silicon So Cs in Microsoft. This position is expected to be highly visible and impactful. The breadth of architectural domains
in our silicon architecture team provides the perfect opportunity to utilize your intellectual curiosity to grow and increase your impact. You will be expected to be on-site at least 50% of the time to help mentor and lead silicon engineers, as well as collaborate with internal customers and partners.
We support and encourage flexible, hybrid work. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone
can thrive at work and beyond. We are committed to a diverse and inclusive workplace and encourage applicants from all backgrounds and walks of life.
Difference makes us better. Qualifications: Required/Minimum Qualifications 9+ years of related technical engineering experience o OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience o OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience o OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.
5+ years of experience in one or more of the following computer architecture fields, in micro-architecture or architecture capacity: CPU or GPU or Machine Learning Accelerator or Network on Chip or Text Compression or Memory subsystems. 3+ years of experience in Machine Learning Accelerator architecture or Micro-Architecture. Familiarity with RTL design. Other Requirements : Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
These requirements include, but are not limited to, the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter. Preferred Qualifications: Ability to work with multiple teams with record of collaboration and leadership. At least one silicon or IP project as architect carried all the way from incubation through silicon bring up and validation. Experience in developing or training or fine tuning ML models, or porting ML models to GPU, CPU, or NPU.
Coding experience in C or C++. Experience analyzing ML models for implementation in ML accelerators. Hardware Engineering IC5 - The typical base pay range for this role across the U. S. is USD $133,600 - $256,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $173,200 - $282,200 per year. Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: careers. /us/en/us-corporate-pay Microsoft is an equal opportunity employer.
All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, interaction (including pregnancy), interactionual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements.
If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the Accommodation request form. Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work. Responsibilities: Lead the architecture and micro-architecture definition of a ML accelerator IP for use in training and inference in various silicon So Cs across Azure and client products. Work with So C architects to incorporate this IP in various silicon solutions.
Author architecture specification of the ML accelerator. Work with software teams to analyze internal and industry standard models and workloads. Translate the computational and data movement needs of the models and workloads to features and specifications of the accelerator. Work with design, verification, and physical design teams to ensure accelerator design meets architecture specification. Continue to update architecture to reflect design changes to meet power, performance, and area goals. Develop architecture models in C/C++ to measure performance and guide the implementation.
Good understanding of number formats and various datatypes to facilitate an area- and power-efficient Hardware (HW)implementation of the compute units of the accelerator. Requisition #: 1635032pca3lyuhf
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