Location: San Jose, CA
Company: Infinera
experience, and location. This role may be eligible for equity grants, discretionary bonuses, or commission payments. The amount of these incentives is based on the terms of the Company's incentive plans, the Company's financial performance, and/or individual employee job performance.
Infinera also offers paid leave, medical, - dental, and vision coverage, 401(k), life, and disability insurance and to eligible employees. Infinera is the global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10
Tier 1 service providers and 6 of the top 7 ICPs. We design, develop, and deliver hardware and software for fiber-based connectivity solutions that span access, aggregation, metro, long haul, and submarine networks.
Our industry-leading, trendsetting edge-to-core solutions provide the foundation for many of the world's largest and most demanding networks that generate billions in service revenue for our customers. The successful candidate shall lead the design efforts of high-speed low-noise clocking circuity, including the fractional-N phase locked loops and the clock distribution networks. Imagine being part of a team that is fundamentally changing the way people communicate, the way
they collaborate, the way they watch TV and explore the universe through the internet.
Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity, and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! The high-quality clocking circuitry is the backbone of the high-speed mixed-signal IPs under development here in Infinera.
You will have the great chance to demonstrate your creativity and superior technical competency by leading the design efforts to help Infinera hold the market leadership. We together will revolutionize the era of efficient high-speed transmission. Essential Functions and Key Responsibilities: Design, simulate, and verify the high frequency fractional-N PLLs. Architect, model, and simulation the noise accumulation and the skew of the clock distribution trees. Model, optimize, and measure the phase noise and jitter performance, and the skew of the whole clocking networks.
Design and implement the high-frequency / low-noise VCOs. Collaborate and/or supervise other team members for system design implementation, layout floor planning, and system level modeling. Mandatory Knowledge/Skills/Abilities: Have exposure in designing low phase noise LC-VCO based PLLs to production. Abundant knowledge in the design trade-offs among different VCO topologies for MM-Wave applications, including but not limited to LC-VCO, TWO, SWO, etc. Hands-on in designing the clock distribution network in Cadence environment. Good at modeling the phase noise and spurs of the frac-N PLLs.
Possess extensive experience in designing and implementing the high frequency VCOs and clock trees with EMX tools. Have a decent understanding in CMOS analog / mixed signal design overall. Preferred Knowledge/Skill/Abilities: Good at supervising testing activities. Fluent in verbal and written communications. Independently resolves issues and conquer design challenges. Self-motivated and detail oriented. Has good interpersonal skills. Education Requirements: M. S. or Ph. D. in E. E. #LI-SR2Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, interaction, color, religion, interactionual orientation, gender identity, national origin, disability status, protected veteran status, or any other characteristic protected by law.
Infinera complies with all applicable state and local laws governing nondiscrimination in employment. Similar Jobs (3) ASIC Design Engineer locations CA, San Jose - Office time type Full time posted on Posted 2 Days Ago ASIC Physical Design Engineer locations 2 Locations time type Full time posted on Posted 16 Days Ago About Us Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet.
Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow.
Come take a look at Infinera! To learn more about working at Infinera visit our main Career page For EU Residents: For additional information about how we handle your personal information, please click here. For CA Residents: For additional information about how we handle your personal information, please click here. Attention Employment Agencies - Thank you for your interest in Infinera. At this time we are not accepting unsolicited resumes from outside agencies. All unsolicited resumes sent to Infinera will be considered our property.
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